PIC24EP512MC206 - Oscillator Configurations.

0.Contents

1.Internal Oscillator - LPRC.

// Configuration registers.
#pragma config ICS = PGD2, JTAGEN = OFF
#pragma config ALTI2C1 = OFF, ALTI2C2 = OFF, WDTWIN = WIN25
#pragma config WDTPOST = PS32768, WDTPRE = PR128, PLLKEN = OFF, WINDIS = OFF, FWDTEN = OFF
#pragma config POSCMD = NONE, OSCIOFNC = OFF, IOL1WAY = OFF, FCKSM = CSDCMD
#pragma config FNOSC = LPRC, PWMLOCK = OFF, IESO = OFF
#pragma config GWRP = OFF, GCP = OFF

#include <xc.h>
// PIC24EP512MC206 - Compile with XC16(v1.33).
// Internal Oscillator - LPRC.

// OSC2 -> Oscilloscope Chanel A.
// RA0  -> Oscilloscope Chanel B.

// Definitions.
#define PROBE				LATAbits.LATA0
#define PROBE_TRIS	TRISAbits.TRISA0

// Main.
int main(void)
{
	// DOZE - Processor Clock Reduction Select bits.
	// DOZE2.0 = 1 1 1 - FCY divided by 128.
	// DOZE2.0 = ...
	// DOZE2.0 = 0 0 0 - FCY divided by 0.
	CLKDIVbits.DOZE2 = 0;
	CLKDIVbits.DOZE1 = 0;
	CLKDIVbits.DOZE0 = 0;
	// DOZEN - Doze Mode Enable bit.
	// DOZEN = 1 - Fcy & Fp ratio specifies with DOZE2.0.
	// DOZEN = 0 - Fcy & Fp ratio forced to 1:1.
	CLKDIVbits.DOZEN = 0;
	// FRCDIV - Internal Fast RC Oscillator Postscaler bits.
	// FRCDIV2.0 = 1 1 1 - FRC divided by 256.
	// FRCDIV2.0 = ...
	// FRCDIV2.0 = 0 0 0 - FRC divided by 1.
	CLKDIVbits.FRCDIV2 = 0;
	CLKDIVbits.FRCDIV1 = 0;
	CLKDIVbits.FRCDIV0 = 0;
	// PLLPOST - PLL VCO Output Divider Select bits.
	// PLLPOST1.0 = 1 1 - Output divided by 8.
	// PLLPOST1.0 = 0 1 - Output divided by 4.
	// PLLPOST1.0 = 0 0 - Output divided by 2.
	CLKDIVbits.PLLPOST1 = 0;
	CLKDIVbits.PLLPOST0 = 0;
	// PLLPRE - PLL Phase Detector Input Divider Select bits.
	// PLLPRE4.0 = 1 1 1 1 1 - Input divided by 33.
	// PLLPRE4.0 = ...
	// PLLPRE4.0 = 0 0 0 0 1 - Input divided by 3.
	// PLLPRE4.0 = 0 0 0 0 0 - Input divided by 2.
	CLKDIVbits.PLLPRE4 = 0;
	CLKDIVbits.PLLPRE3 = 0;
	CLKDIVbits.PLLPRE2 = 0;
	CLKDIVbits.PLLPRE1 = 0;
	CLKDIVbits.PLLPRE0 = 0;
	// PLLDIV - PLL Feedback Divisor bits.
	// PLLDIV8.0 = 1 1 1 1 1 1 1 1 1 - 513.
	// PLLDIV8.0 = ...
	// PLLDIV8.0 = 0 0 0 1 1 0 0 0 0 - 50.
	// PLLDIV8.0 = ...
	// PLLDIV8.0 = 0 0 0 0 0 0 0 0 1 - 3.
	// PLLDIV8.0 = 0 0 0 0 0 0 0 0 0 - 2.
	PLLFBDbits.PLLDIV8 = 0;
	PLLFBDbits.PLLDIV7 = 0;
	PLLFBDbits.PLLDIV6 = 0;
	PLLFBDbits.PLLDIV5 = 0;
	PLLFBDbits.PLLDIV4 = 0;
	PLLFBDbits.PLLDIV3 = 0;
	PLLFBDbits.PLLDIV2 = 0;
	PLLFBDbits.PLLDIV1 = 0;
	PLLFBDbits.PLLDIV0 = 0;

	// TUN - FRC Oscillator Tuning bits.
	// TUN5.0 = 0 1 1 1 1 1 - Maximum frequency deviation of 1.453% (7.477 MHz).
	// TUN5.0 = 0 1 1 1 1 0 - Center frequency +1.406% (7.474 MHz).
	// TUN5.0 = ...
	// TUN5.0 = 0 0 0 0 0 1 - Center frequency +0.047% (7.373 MHz).
	// TUN5.0 = 0 0 0 0 0 0 - Center frequency (7.37 MHz nominal).
	// TUN5.0 = 1 1 1 1 1 1 - Center frequency –0.047% (7.367 MHz).
	// TUN5.0 = ...
	// TUN5.0 = 1 0 0 0 0 1 - Center frequency –1.453% (7.263 MHz).
	// TUN5.0 = 1 0 0 0 0 0 - Minimum frequency deviation of -1.5% (7.259 MHz).
	OSCTUNbits.TUN5 = 0;
	OSCTUNbits.TUN4 = 0;
	OSCTUNbits.TUN3 = 0;
	OSCTUNbits.TUN2 = 0;
	OSCTUNbits.TUN1 = 0;
	OSCTUNbits.TUN0 = 0;

	PROBE = 0x0000;
	PROBE_TRIS = 0x0000;

	while(1){
		PROBE ^= 0x0001;
	}
	return(0);
}

Fosc ~ 16kHz - DOZE2.0 = 0 0 0 - DOZEN = 0
Fosc ~ 125Hz - DOZE2.0 = 1 1 1 - DOZEN = 1

2.Internal Oscillator - FRC.

// Configuration registers.
#pragma config ICS = PGD2, JTAGEN = OFF
#pragma config ALTI2C1 = OFF, ALTI2C2 = OFF, WDTWIN = WIN25
#pragma config WDTPOST = PS32768, WDTPRE = PR128, PLLKEN = OFF, WINDIS = OFF, FWDTEN = OFF
#pragma config POSCMD = NONE, OSCIOFNC = OFF, IOL1WAY = OFF, FCKSM = CSDCMD
#pragma config FNOSC = FRC, PWMLOCK = OFF, IESO = OFF
#pragma config GWRP = OFF, GCP = OFF

#include <xc.h>
// PIC24EP512MC206 - Compile with XC16(v1.33).
// Internal Oscillator - FRC.

// OSC2 -> Oscilloscope Chanel A.
// RA0  -> Oscilloscope Chanel B.

// Definitions.
#define PROBE				LATAbits.LATA0
#define PROBE_TRIS	TRISAbits.TRISA0

// Main.
int main(void)
{
	// DOZE - Processor Clock Reduction Select bits.
	// DOZE2.0 = 1 1 1 - FCY divided by 128.
	// DOZE2.0 = ...
	// DOZE2.0 = 0 0 0 - FCY divided by 0.
	CLKDIVbits.DOZE2 = 0;
	CLKDIVbits.DOZE1 = 0;
	CLKDIVbits.DOZE0 = 0;
	// DOZEN - Doze Mode Enable bit.
	// DOZEN = 1 - Fcy & Fp ratio specifies with DOZE2.0.
	// DOZEN = 0 - Fcy & Fp ratio forced to 1:1.
	CLKDIVbits.DOZEN = 0;
	// FRCDIV - Internal Fast RC Oscillator Postscaler bits.
	// FRCDIV2.0 = 1 1 1 - FRC divided by 256.
	// FRCDIV2.0 = ...
	// FRCDIV2.0 = 0 0 0 - FRC divided by 1.
	CLKDIVbits.FRCDIV2 = 0;
	CLKDIVbits.FRCDIV1 = 0;
	CLKDIVbits.FRCDIV0 = 0;
	// PLLPOST - PLL VCO Output Divider Select bits.
	// PLLPOST1.0 = 1 1 - Output divided by 8.
	// PLLPOST1.0 = 0 1 - Output divided by 4.
	// PLLPOST1.0 = 0 0 - Output divided by 2.
	CLKDIVbits.PLLPOST1 = 0;
	CLKDIVbits.PLLPOST0 = 0;
	// PLLPRE - PLL Phase Detector Input Divider Select bits.
	// PLLPRE4.0 = 1 1 1 1 1 - Input divided by 33.
	// PLLPRE4.0 = ...
	// PLLPRE4.0 = 0 0 0 0 1 - Input divided by 3.
	// PLLPRE4.0 = 0 0 0 0 0 - Input divided by 2.
	CLKDIVbits.PLLPRE4 = 0;
	CLKDIVbits.PLLPRE3 = 0;
	CLKDIVbits.PLLPRE2 = 0;
	CLKDIVbits.PLLPRE1 = 0;
	CLKDIVbits.PLLPRE0 = 0;
	// PLLDIV - PLL Feedback Divisor bits.
	// PLLDIV8.0 = 1 1 1 1 1 1 1 1 1 - 513.
	// PLLDIV8.0 = ...
	// PLLDIV8.0 = 0 0 0 1 1 0 0 0 0 - 50.
	// PLLDIV8.0 = ...
	// PLLDIV8.0 = 0 0 0 0 0 0 0 0 1 - 3.
	// PLLDIV8.0 = 0 0 0 0 0 0 0 0 0 - 2.
	PLLFBDbits.PLLDIV8 = 0;
	PLLFBDbits.PLLDIV7 = 0;
	PLLFBDbits.PLLDIV6 = 0;
	PLLFBDbits.PLLDIV5 = 0;
	PLLFBDbits.PLLDIV4 = 0;
	PLLFBDbits.PLLDIV3 = 0;
	PLLFBDbits.PLLDIV2 = 0;
	PLLFBDbits.PLLDIV1 = 0;
	PLLFBDbits.PLLDIV0 = 0;

	// TUN - FRC Oscillator Tuning bits.
	// TUN5.0 = 0 1 1 1 1 1 - Maximum frequency deviation of 1.453% (7.477 MHz).
	// TUN5.0 = 0 1 1 1 1 0 - Center frequency +1.406% (7.474 MHz).
	// TUN5.0 = ...
	// TUN5.0 = 0 0 0 0 0 1 - Center frequency +0.047% (7.373 MHz).
	// TUN5.0 = 0 0 0 0 0 0 - Center frequency (7.37 MHz nominal).
	// TUN5.0 = 1 1 1 1 1 1 - Center frequency –0.047% (7.367 MHz).
	// TUN5.0 = ...
	// TUN5.0 = 1 0 0 0 0 1 - Center frequency –1.453% (7.263 MHz).
	// TUN5.0 = 1 0 0 0 0 0 - Minimum frequency deviation of -1.5% (7.259 MHz).
	OSCTUNbits.TUN5 = 0;
	OSCTUNbits.TUN4 = 0;
	OSCTUNbits.TUN3 = 0;
	OSCTUNbits.TUN2 = 0;
	OSCTUNbits.TUN1 = 0;
	OSCTUNbits.TUN0 = 0;

	PROBE = 0x0000;
	PROBE_TRIS = 0x0000;

	while(1){
		PROBE ^= 0x0001;
	}
	return(0);
}

Fosc ~ 16kHz - DOZE2.0 = 0 0 0 - DOZEN = 0
Fosc ~ 125Hz - DOZE2.0 = 1 1 1 - DOZEN = 1

3.Internal Oscillator - FRCDIV16 - Oscillator Switching.

// Configuration registers.
#pragma config ICS = PGD2, JTAGEN = OFF
#pragma config ALTI2C1 = OFF, ALTI2C2 = OFF, WDTWIN = WIN25
#pragma config WDTPOST = PS32768, WDTPRE = PR128, PLLKEN = OFF, WINDIS = OFF, FWDTEN = OFF
#pragma config POSCMD = NONE, OSCIOFNC = OFF, IOL1WAY = OFF, FCKSM = CSECMD
#pragma config FNOSC = FRC, PWMLOCK = OFF, IESO = OFF
#pragma config GWRP = OFF, GCP = OFF

#include <xc.h>
// PIC24EP512MC206 - Compile with XC16(v1.33).
// Internal Oscillator - FRCDIV16 - Oscillator Switching.

// Definitions.
#define PROBE		LATAbits.LATA0
#define PROBE_TRIS	TRISAbits.TRISA0

// Main.
int main(void)
{
	// DOZE - Processor Clock Reduction Select bits.
	// DOZE2.0 = 1 1 1 - FCY divided by 128.
	// DOZE2.0 = ...
	// DOZE2.0 = 0 0 0 - FCY divided by 0.
	CLKDIVbits.DOZE2 = 0;
	CLKDIVbits.DOZE1 = 0;
	CLKDIVbits.DOZE0 = 0;
	// DOZEN - Doze Mode Enable bit.
	// DOZEN = 1 - Fcy & Fp ratio specifies with DOZE2.0.
	// DOZEN = 0 - Fcy & Fp ratio forced to 1:1.
	CLKDIVbits.DOZEN = 0;
	// FRCDIV - Internal Fast RC Oscillator Postscaler bits.
	// FRCDIV2.0 = 1 1 1 - FRC divided by 256.
	// FRCDIV2.0 = ...
	// FRCDIV2.0 = 0 0 0 - FRC divided by 1.
	CLKDIVbits.FRCDIV2 = 0;
	CLKDIVbits.FRCDIV1 = 0;
	CLKDIVbits.FRCDIV0 = 0;
	// PLLPOST - PLL VCO Output Divider Select bits.
	// PLLPOST1.0 = 1 1 - Output divided by 8.
	// PLLPOST1.0 = 0 1 - Output divided by 4.
	// PLLPOST1.0 = 0 0 - Output divided by 2.
	CLKDIVbits.PLLPOST1 = 0;
	CLKDIVbits.PLLPOST0 = 0;
	// PLLPRE - PLL Phase Detector Input Divider Select bits.
	// PLLPRE4.0 = 1 1 1 1 1 - Input divided by 33.
	// PLLPRE4.0 = ...
	// PLLPRE4.0 = 0 0 0 0 1 - Input divided by 3.
	// PLLPRE4.0 = 0 0 0 0 0 - Input divided by 2.
	CLKDIVbits.PLLPRE4 = 0;
	CLKDIVbits.PLLPRE3 = 0;
	CLKDIVbits.PLLPRE2 = 0;
	CLKDIVbits.PLLPRE1 = 0;
	CLKDIVbits.PLLPRE0 = 0;
	// PLLDIV - PLL Feedback Divisor bits.
	// PLLDIV8.0 = 1 1 1 1 1 1 1 1 1 - 513.
	// PLLDIV8.0 = ...
	// PLLDIV8.0 = 0 0 0 1 1 0 0 0 0 - 50.
	// PLLDIV8.0 = ...
	// PLLDIV8.0 = 0 0 0 0 0 0 0 0 1 - 3.
	// PLLDIV8.0 = 0 0 0 0 0 0 0 0 0 - 2.
	PLLFBDbits.PLLDIV8 = 0;
	PLLFBDbits.PLLDIV7 = 0;
	PLLFBDbits.PLLDIV6 = 0;
	PLLFBDbits.PLLDIV5 = 0;
	PLLFBDbits.PLLDIV4 = 0;
	PLLFBDbits.PLLDIV3 = 0;
	PLLFBDbits.PLLDIV2 = 0;
	PLLFBDbits.PLLDIV1 = 0;
	PLLFBDbits.PLLDIV0 = 0;

	// TUN - FRC Oscillator Tuning bits.
	// TUN5.0 = 0 1 1 1 1 1 - Maximum frequency deviation of 1.453% (7.477 MHz).
	// TUN5.0 = 0 1 1 1 1 0 - Center frequency +1.406% (7.474 MHz).
	// TUN5.0 = ...
	// TUN5.0 = 0 0 0 0 0 1 - Center frequency +0.047% (7.373 MHz).
	// TUN5.0 = 0 0 0 0 0 0 - Center frequency (7.37 MHz nominal).
	// TUN5.0 = 1 1 1 1 1 1 - Center frequency –0.047% (7.367 MHz).
	// TUN5.0 = ...
	// TUN5.0 = 1 0 0 0 0 1 - Center frequency –1.453% (7.263 MHz).
	// TUN5.0 = 1 0 0 0 0 0 - Minimum frequency deviation of -1.5% (7.259 MHz).
	OSCTUNbits.TUN5 = 0;
	OSCTUNbits.TUN4 = 0;
	OSCTUNbits.TUN3 = 0;
	OSCTUNbits.TUN2 = 0;
	OSCTUNbits.TUN1 = 0;
	OSCTUNbits.TUN0 = 0;

	// Oscillator Switching.
	// Initiate Clock Switch to FRCDIV16 (OSCCON.NOSC=0b110).
	__builtin_write_OSCCONH(0x06);
	// Start clock switching OSCCON.OSWEN = 1.
	__builtin_write_OSCCONL(0x01);
	// Wait for Clock switch to occur (COSC = 0b110).
	while (OSCCONbits.COSC != 0b110);
	
	PROBE = 0x0000;
	PROBE_TRIS = 0x0000;

	while(1){
		PROBE ^= 0x0001;
	}
	return(0);
}

Fosc ~ 230kHz - DOZE2.0 = 0 0 0 - DOZEN = 0
Fosc ~ 1.8kHz - DOZE2.0 = 1 1 1 - DOZEN = 1

4.Internal Oscillator - FRCDIVN.

// Configuration registers.
#pragma config ICS = PGD2, JTAGEN = OFF
#pragma config ALTI2C1 = OFF, ALTI2C2 = OFF, WDTWIN = WIN25
#pragma config WDTPOST = PS32768, WDTPRE = PR128, PLLKEN = OFF, WINDIS = OFF, FWDTEN = OFF
#pragma config POSCMD = NONE, OSCIOFNC = OFF, IOL1WAY = OFF, FCKSM = CSDCMD
#pragma config FNOSC = FRCDIVN, PWMLOCK = OFF, IESO = OFF
#pragma config GWRP = OFF, GCP = OFF

#include <xc.h>
// PIC24EP512MC206 - Compile with XC16(v1.33).
// Internal Oscillator - FRCDIVN.

// OSC2 -> Oscilloscope Chanel A.
// RA0  -> Oscilloscope Chanel B.

// Definitions.
#define PROBE				LATAbits.LATA0
#define PROBE_TRIS	TRISAbits.TRISA0

// Main.
int main(void)
{
	// DOZE - Processor Clock Reduction Select bits.
	// DOZE2.0 = 1 1 1 - FCY divided by 128.
	// DOZE2.0 = ...
	// DOZE2.0 = 0 0 0 - FCY divided by 0.
	CLKDIVbits.DOZE2 = 0;
	CLKDIVbits.DOZE1 = 0;
	CLKDIVbits.DOZE0 = 0;
	// DOZEN - Doze Mode Enable bit.
	// DOZEN = 1 - Fcy & Fp ratio specifies with DOZE2.0.
	// DOZEN = 0 - Fcy & Fp ratio forced to 1:1.
	CLKDIVbits.DOZEN = 0;
	// FRCDIV - Internal Fast RC Oscillator Postscaler bits.
	// FRCDIV2.0 = 1 1 1 - FRC divided by 256.
	// FRCDIV2.0 = ...
	// FRCDIV2.0 = 0 0 0 - FRC divided by 1.
	CLKDIVbits.FRCDIV2 = 0;
	CLKDIVbits.FRCDIV1 = 0;
	CLKDIVbits.FRCDIV0 = 0;
	// PLLPOST - PLL VCO Output Divider Select bits.
	// PLLPOST1.0 = 1 1 - Output divided by 8.
	// PLLPOST1.0 = 0 1 - Output divided by 4.
	// PLLPOST1.0 = 0 0 - Output divided by 2.
	CLKDIVbits.PLLPOST1 = 0;
	CLKDIVbits.PLLPOST0 = 0;
	// PLLPRE - PLL Phase Detector Input Divider Select bits.
	// PLLPRE4.0 = 1 1 1 1 1 - Input divided by 33.
	// PLLPRE4.0 = ...
	// PLLPRE4.0 = 0 0 0 0 1 - Input divided by 3.
	// PLLPRE4.0 = 0 0 0 0 0 - Input divided by 2.
	CLKDIVbits.PLLPRE4 = 0;
	CLKDIVbits.PLLPRE3 = 0;
	CLKDIVbits.PLLPRE2 = 0;
	CLKDIVbits.PLLPRE1 = 0;
	CLKDIVbits.PLLPRE0 = 0;
	// PLLDIV - PLL Feedback Divisor bits.
	// PLLDIV8.0 = 1 1 1 1 1 1 1 1 1 - 513.
	// PLLDIV8.0 = ...
	// PLLDIV8.0 = 0 0 0 1 1 0 0 0 0 - 50.
	// PLLDIV8.0 = ...
	// PLLDIV8.0 = 0 0 0 0 0 0 0 0 1 - 3.
	// PLLDIV8.0 = 0 0 0 0 0 0 0 0 0 - 2.
	PLLFBDbits.PLLDIV8 = 0;
	PLLFBDbits.PLLDIV7 = 0;
	PLLFBDbits.PLLDIV6 = 0;
	PLLFBDbits.PLLDIV5 = 0;
	PLLFBDbits.PLLDIV4 = 0;
	PLLFBDbits.PLLDIV3 = 0;
	PLLFBDbits.PLLDIV2 = 0;
	PLLFBDbits.PLLDIV1 = 0;
	PLLFBDbits.PLLDIV0 = 0;

	// TUN - FRC Oscillator Tuning bits.
	// TUN5.0 = 0 1 1 1 1 1 - Maximum frequency deviation of 1.453% (7.477 MHz).
	// TUN5.0 = 0 1 1 1 1 0 - Center frequency +1.406% (7.474 MHz).
	// TUN5.0 = ...
	// TUN5.0 = 0 0 0 0 0 1 - Center frequency +0.047% (7.373 MHz).
	// TUN5.0 = 0 0 0 0 0 0 - Center frequency (7.37 MHz nominal).
	// TUN5.0 = 1 1 1 1 1 1 - Center frequency –0.047% (7.367 MHz).
	// TUN5.0 = ...
	// TUN5.0 = 1 0 0 0 0 1 - Center frequency –1.453% (7.263 MHz).
	// TUN5.0 = 1 0 0 0 0 0 - Minimum frequency deviation of -1.5% (7.259 MHz).
	OSCTUNbits.TUN5 = 0;
	OSCTUNbits.TUN4 = 0;
	OSCTUNbits.TUN3 = 0;
	OSCTUNbits.TUN2 = 0;
	OSCTUNbits.TUN1 = 0;
	OSCTUNbits.TUN0 = 0;

	PROBE = 0x0000;
	PROBE_TRIS = 0x0000;

	while(1){
		PROBE ^= 0x0001;
	}
	return(0);
}

Fosc ~ 3.7MHz - FRCDIV2.0 = 0 0 0 - DOZE2.0 = 0 0 0 - DOZEN = 0
Fosc ~ 28kHz - FRCDIV2.0 = 0 0 0 - DOZE2.0 = 1 1 1 - DOZEN = 1
Fosc ~ 14kHz - FRCDIV2.0 = 1 1 1 - DOZE2.0 = 0 0 0 - DOZEN = 0
Fosc ~ 110Hz - FRCDIV2.0 = 1 1 1 - DOZE2.0 = 1 1 1 - DOZEN = 1

5.Internal Oscillator - FRCPLL.

// Configuration registers.
#pragma config ICS = PGD2, JTAGEN = OFF
#pragma config ALTI2C1 = OFF, ALTI2C2 = OFF, WDTWIN = WIN25
#pragma config WDTPOST = PS32768, WDTPRE = PR128, PLLKEN = OFF, WINDIS = OFF, FWDTEN = OFF
#pragma config POSCMD = NONE, OSCIOFNC = OFF, IOL1WAY = OFF, FCKSM = CSDCMD
#pragma config FNOSC = FRCPLL, PWMLOCK = OFF, IESO = OFF
#pragma config GWRP = OFF, GCP = OFF

#include <xc.h>
// PIC24EP512MC206 - Compile with XC16(v1.33).
// Internal Oscillator - FRCPLL.

// OSC2 -> Oscilloscope Chanel A.
// RA0  -> Oscilloscope Chanel B.

// Definitions.
#define PROBE				LATAbits.LATA0
#define PROBE_TRIS	TRISAbits.TRISA0

// Main.
int main(void)
{
	// DOZE - Processor Clock Reduction Select bits.
	// DOZE2.0 = 1 1 1 - FCY divided by 128.
	// DOZE2.0 = ...
	// DOZE2.0 = 0 0 0 - FCY divided by 0.
	CLKDIVbits.DOZE2 = 0;
	CLKDIVbits.DOZE1 = 0;
	CLKDIVbits.DOZE0 = 0;
	// DOZEN - Doze Mode Enable bit.
	// DOZEN = 1 - Fcy & Fp ratio specifies with DOZE2.0.
	// DOZEN = 0 - Fcy & Fp ratio forced to 1:1.
	CLKDIVbits.DOZEN = 0;
	// FRCDIV - Internal Fast RC Oscillator Postscaler bits.
	// FRCDIV2.0 = 1 1 1 - FRC divided by 256.
	// FRCDIV2.0 = ...
	// FRCDIV2.0 = 0 0 0 - FRC divided by 1.
	CLKDIVbits.FRCDIV2 = 0;
	CLKDIVbits.FRCDIV1 = 0;
	CLKDIVbits.FRCDIV0 = 0;
	// PLLPOST - PLL VCO Output Divider Select bits.
	// PLLPOST1.0 = 1 1 - Output divided by 8.
	// PLLPOST1.0 = 0 1 - Output divided by 4.
	// PLLPOST1.0 = 0 0 - Output divided by 2.
	CLKDIVbits.PLLPOST1 = 0;
	CLKDIVbits.PLLPOST0 = 0;
	// PLLPRE - PLL Phase Detector Input Divider Select bits.
	// PLLPRE4.0 = 1 1 1 1 1 - Input divided by 33.
	// PLLPRE4.0 = ...
	// PLLPRE4.0 = 0 0 0 0 1 - Input divided by 3.
	// PLLPRE4.0 = 0 0 0 0 0 - Input divided by 2.
	CLKDIVbits.PLLPRE4 = 0;
	CLKDIVbits.PLLPRE3 = 0;
	CLKDIVbits.PLLPRE2 = 0;
	CLKDIVbits.PLLPRE1 = 0;
	CLKDIVbits.PLLPRE0 = 0;
	// PLLDIV - PLL Feedback Divisor bits.
	// PLLDIV8.0 = 1 1 1 1 1 1 1 1 1 - 513.
	// PLLDIV8.0 = ...
	// PLLDIV8.0 = 0 0 0 1 1 0 0 0 0 - 50.
	// PLLDIV8.0 = ...
	// PLLDIV8.0 = 0 0 0 0 0 0 0 0 1 - 3.
	// PLLDIV8.0 = 0 0 0 0 0 0 0 0 0 - 2.
	PLLFBDbits.PLLDIV8 = 1;
	PLLFBDbits.PLLDIV7 = 1;
	PLLFBDbits.PLLDIV6 = 1;
	PLLFBDbits.PLLDIV5 = 1;
	PLLFBDbits.PLLDIV4 = 1;
	PLLFBDbits.PLLDIV3 = 1;
	PLLFBDbits.PLLDIV2 = 1;
	PLLFBDbits.PLLDIV1 = 1;
	PLLFBDbits.PLLDIV0 = 1;

	// TUN - FRC Oscillator Tuning bits.
	// TUN5.0 = 0 1 1 1 1 1 - Maximum frequency deviation of 1.453% (7.477 MHz).
	// TUN5.0 = 0 1 1 1 1 0 - Center frequency +1.406% (7.474 MHz).
	// TUN5.0 = ...
	// TUN5.0 = 0 0 0 0 0 1 - Center frequency +0.047% (7.373 MHz).
	// TUN5.0 = 0 0 0 0 0 0 - Center frequency (7.37 MHz nominal).
	// TUN5.0 = 1 1 1 1 1 1 - Center frequency –0.047% (7.367 MHz).
	// TUN5.0 = ...
	// TUN5.0 = 1 0 0 0 0 1 - Center frequency –1.453% (7.263 MHz).
	// TUN5.0 = 1 0 0 0 0 0 - Minimum frequency deviation of -1.5% (7.259 MHz).
	OSCTUNbits.TUN5 = 0;
	OSCTUNbits.TUN4 = 0;
	OSCTUNbits.TUN3 = 0;
	OSCTUNbits.TUN2 = 0;
	OSCTUNbits.TUN1 = 0;
	OSCTUNbits.TUN0 = 0;

	PROBE = 0x0000;
	PROBE_TRIS = 0x0000;

	while(1){
		PROBE ^= 0x0001;
	}
	return(0);
}

11.2017